IEEE/CPMT Lunch Meeting, in the Santa Clara Valley:

    Considerations for Advancing Technology in Computer System Packaging
    -- Dale Becker, Ph.D., IBM Corp., Poughkeepsie, NY

Thursday, October 22, 2015

• Optional lunch provided ($5 for IEEE members, all students, all unemployed; $10 for non-members)
• For lunch, please bring a $5 or $10 bill
• Registration and (optional lunch) at 11:30 AM
• Presentation (no cost) at 12:00 noon (come at 11:45 AM)
• Please reserve by the end of October 20, so we can provide the food.

Please register in advance for this event, using our CPMT Chapter's EventBrite registration site.

You may register yourself, plus others from your company/institution, for this lunch and presentation. Please make an on-line payment for the lunch.



LOCATION: Texas Instruments Building E Conference Center
    2900 Semiconductor Dr. (off Kifer Rd), Santa Clara -- click map at right.

OVERVIEW:

    In this era of smart computing, big data and deep analytics define the architecture of computers and the software that runs on these systems. The hardware technology is evolving to support the needs of the systems under the constraints of decreasing cost per performance metric, increasing bandwidth per unit area and constant power per unit volume from one generation of systems to the next. To meet these constraints, the trade-offs of proposed solutions need to be evaluated. As a pair of examples, 3D integration provides the possibility of higher compute density and data bandwidth at the challenge of maintaining power density and cost constraints, and integrated voltage regulation provides the possibility of maintaining power density with the challenge of maintaining compute density and cost constraints. This presentation will discuss the application of new technology that address design challenges and the tradeoffs that are encountered.

Speaker Biography:

    Dale Becker received the B.E.E degree from the University of Minnesota, M.S.E.E. from Syracuse University and the Ph.D. from the University of Illinois at Urbana Champaign. He is a Distinguished Engineer in IBM Systems and Technology Group and a member of the IBM Academy of Technology. He is the System Electrical Architect for the IBM POWER and System Z Enterprise Systems. His responsibilities include designing the high-speed channels to enable the computer system's performance and the power distribution networks for reliable operation of the integrated circuits that make up the processor subsystem.
    Dr. Becker is the Co-Chair of the IEEE EPEPS 2015 Conference and was co-chair of the 2014 IEEE EMCS embedded conference on SIPI TPC and 2015 EMCS-US Global University. He has over 25 patents on electrical design of computer systems and has presented over 75 papers in refereed journals and international conferences covering many aspects of electrical computer system design including power distribution analysis and design and modeling of signal and power distribution networks. He is a Fellow of IEEE, an iNEMI Technical Committee member and a member of IMAPS and SWE.