IEEE/CPMT Lunch Meeting, in the Santa Clara Valley:

    Recent Advances and Trends in Semiconductor Packaging
    -- Dr. John H. Lau, Sr. Technical Advisor, ASM

Tuesday, April 12, 2016

• Optional lunch provided ($10 for non-members, $5 for IEEE members/students/unemployed)
• Registration (and sandwiches/drinks) at 11:30 AM
• Presentation-only (no cost) at 12:00 PM noon (come at 11:45 AM)
• Please reserve by the end of April 10, so we can provide the food.
• We welcome those looking for employment to come to our meetings and bring copies of your resume with you. We will have a table set up for you to sit and network with others.

Please register in advance for this event, using our CPMT Chapter's EventBrite registration site.

You may register yourself, plus others from your company/institution, for this lunch and presentation. Please make an on-line payment for the lunch.



LOCATION: Texas Instruments Building E Conference Center
    2900 Semiconductor Dr. (off Kifer Rd), Santa Clara -- click map at right.

OVERVIEW:

    Recent advances in, for example, fan-out wafer/panel level packaging (TSMC's InFO-WLP and IZM's FO-PLP), 3D IC packaging (TSMC's InFO_PoP vs. Samsung's ePoP), 3D IC integration (Hynix/Samsung's HBM for AMD/NVIDIA's GPU vs. Micron's HMC for Intel's Knights Landing CPU), 2.5D IC Integration (TSV-less interconnects and interposers), embedded 3D hybrid integration (of VCSEL, driver, serializer, polymer waveguide, etc.), 3D CIS/IC integration, and 3D MEMS/IC integration are examined and their new trends will be discussed in this lecture. The patents impacting the semiconductor packaging the most (so far) will be mentioned first and the patent issues of fan-out wafer/panel-level will be discussed and some recommendations will be made.

Speaker Biography:

    John H. Lau has been a Sr. Technical Advisor of ASM since July 2014. Prior to that, he was a Senior Scientist/MTS at Hewlett-Packard/Agilent for more than 25 years. With more than 38 years of R&D and manufacturing experience, he has published more than 440 peer-reviewed papers, 30 issued and pending patents, and 20 textbooks on, e.g., Reliability of RoHS compliant 2D and 3D IC Interconnects (2011), TSV for 3D Integration (2013), and 3D IC Integration and Packaging (2015). He is an IEEE Fellow and ASME Fellow.