IEEE/CPMT Lunch Meeting, in the Santa Clara Valley:

    Increased Power Density and Simplified Designs with 3-D SiP Module
    -- Jim Moss, Texas Instruments

• Optional lunch provided ($10 for non-members, $5 for IEEE members/students/unemployed)
• Registration (and sandwiches/drinks) at 11:30 AM
• Presentation-only (no cost) at 12:00 PM noon (come at 11:45 AM)
• Please reserve by the end of May 8, so we can provide the food.
• We welcome those looking for employment to bring copies of your resume with you. We will have a table set up for you to sit and network with others.

Please register in advance for this event, using our CPMT Chapter's EventBrite registration site.

You may register yourself, plus others from your company/institution, for this lunch and presentation. Please make an on-line payment for the lunch.



LOCATION: Texas Instruments Building E Conference Center
    2900 Semiconductor Dr. (off Kifer Rd), Santa Clara -- click map at right.

OVERVIEW:

    This talk will discuss volumetric co-design methodology and packaging construction trade-offs for 3D SiP power modules. It will provide more details on the SiP eco-system, co-design, construction, materials and circuit topology.
    Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more real estate toward end-user applications – all with less space allocated to power management where not just the X-Y shrink but the 3D volumetric shrink is required also. For example, in wearable products, the semiconductor industry has recently seen an increase in the use of system-in-package (SiP) technology for users who want simpler, more flexible designs and need to fulfill challenging space requirements. And, we expect to see this trend continue.

Speaker Biography:

    Jim Moss is the Power Products Technology Manager in TI's Silicon Valley Analog. He is currently working on high-power modules utilizing controllers, MOS & GaN FETs, and passives. He has over 35 years of experience in the semiconductor industry and with TI/National for more than 25 years.
    His experience covers Power, Wireless/RF, x86, and microcontrollers. He has been working in Systems Design, Product, Test and various technical management roles. He holds an MS-EM from Santa Clara University and BS-EE from Illinois Institute of Technology.