Although billions of connections can be simultaneously made in one photolithographic step, all interconnections must reside in the same plane. Inevitably, 3-dimentional interconnection technology must be developed to minimize the signal path. The concept is not new, however efficiently forming vias in the semiconductor wafers has remained unsatisfactory until recently because of fabrication complexity resulting in poor yields. Tru-Si Technology has introduced a new process, based on atmospheric downstream plasma (ADP) which produces a dry chemical etching (DCE). When ADP is applied to the back of silicon wafers, the rates of silicon removal allow an efficient thinning of the wafers. In this new process, there is no mechanical stress causing breakage of the thin wafers or messy chemicals to contend with. Taking advantage of its unique ability to produce very thin silicon wafers at high yield, Tru-Si Technology is developing a 3-dimensional wafer level packaging technology. ADP etching uses a mask to etch vias in the silicon. The vias are produced in two self-aligning steps by etching the front of the wafer followed by deposition of a dielectric and metallization. The back of the wafer is then ADP etched. Wafers interconnected through vias can be stacked to form a 3-dimentional network.
This work leads to the development of 3-D wafer level packaging where stacks of dies are separated after stacking.
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Revised
30 June 2000