Components, Packaging & Manufacturing Technology Society

IEEE/CPMT Dinner Meeting:

"Wafer Thinning & Die Stacking for Vertical Packaging" --
John Reche, Tru-Si; and Marc Robinson, Vertical Circuits

Wednesday, May 10, 2000
Subsidized buffet dinner ($15 if reserved before May 6; $20 after & at door) served at 6:30; Presentation (no cost) at 7:30.
Embassy Suites Hotel, 2885 Lakeside Drive (101 at Bowers Ave), Santa Clara -- see map.
PLEASE RSVP (for dinner and/or meeting) by email to Tom Tarter, or call our CPMT hotline at 800-686-9366.

Wafer Thinning (Slides, in PDF format - 3MB)
Since its inception in 1959, the integrated circuit has evolved into an extremely complex wiring technology on semiconductor substrates. As a consequence of the dramatic increase in switching speed of active devices, interconnection propagation delays have become the major obstacle to higher operational speed.

Although billions of connections can be simultaneously made in one photolithographic step, all interconnections must reside in the same plane. Inevitably, 3-dimentional interconnection technology must be developed to minimize the signal path. The concept is not new, however efficiently forming vias in the semiconductor wafers has remained unsatisfactory until recently because of fabrication complexity resulting in poor yields. Tru-Si Technology has introduced a new process, based on atmospheric downstream plasma (ADP) which produces a dry chemical etching (DCE). When ADP is applied to the back of silicon wafers, the rates of silicon removal allow an efficient thinning of the wafers. In this new process, there is no mechanical stress causing breakage of the thin wafers or messy chemicals to contend with. Taking advantage of its unique ability to produce very thin silicon wafers at high yield, Tru-Si Technology is developing a 3-dimensional wafer level packaging technology. ADP etching uses a mask to etch vias in the silicon. The vias are produced in two self-aligning steps by etching the front of the wafer followed by deposition of a dielectric and metallization. The back of the wafer is then ADP etched. Wafers interconnected through vias can be stacked to form a 3-dimentional network.

This work leads to the development of 3-D wafer level packaging where stacks of dies are separated after stacking.

Vertical Stacking of IC Die (Slides, in PPT format - 11MB)
Dense packaging of integrated circuits is required for use in many of today's electronic products such as cellular phones, personal digital assistants, portable electronic systems, satellites, military avionics, and other portable systems. Deep submicron integrated circuit technology is enabling system on a chip (SOC) capabilities for today's system designers. However, there are still situations that preclude the use of system on a chip technology. These arise from requirements for electrical noise isolation, RF isolation, or semiconductor process incompatibility resulting from subsystem integrated circuit process requirements. Vertical Circuits Inc. (VCI) technology allows designers to stack system components inside one package to provide a "system in a socket" capability. This stacked multichip package (MCP) technology uses a patented Vertical Interconnection Process (VIP) and/or Direct Contact Process (DCP). In some cases, a chip-scale package (CSP) containing stacked die can be smaller than if all functions were included on one integrated circuit die! VCI, a TRW affiliate company, was formed by the merger of Cubic Memory, Inc., and TRW Components International (TRWCI). VCI is focused on high density products for the mil/aerospace and commercial markets, and is manufacturing fully molded stacked die in unique and semi-standard BGA and TSOP packages.

Speaker Biographies:
John Reche is Director of Advanced Packaging at Tru-Si Technologies in Sunnyvale, CA. His responsibilities include design and implementation of the novel 3-dimentional Thru-Silicon wafer interconnect. John has recently assembled a thin-film lab in order to shorten the development time and experiment with materials and services difficult to procure by subcontract. In addition to the Atmospheric Downstream Plasma etching equipment, Tru-Si can sputter thin-films, do front and back photolithography on 6 and 8" wafers and align stacked wafers for bonding.
John has twenty years experience in building microwave thin-film modules, magneto-optic devices and MCM-D. He has worked in large corporations such as Litton and GTE as well as several start-up companies. John has worked as independent consultant for many years. He founded a Silicon on Silicon Multichip modules company in the late 80's which pioneered high-speed digital interconnects.
John has published and presented over 60 technical papers at technical meetings.

Marc Robinson, Vertical Circuits
Marc Robinson joined Vertical Circuits Incorporated (VCI) as Vice President, Engineering & Operations in 1996. Prior to joining VCI (formerly known as Cubic Memory) Mr. Robinson was with Sierra Semiconductor as Vice President, Technology Development and Quality. With GEC Plessey Semiconductors, Inc. from 1990 to 1995, he served as Vice President, TQM and Quality, as Vice President, Engineering, and as the Technical Executive for North America. From 1985 to 1990 Marc served as a Business Unit Director at IMP, Inc. Mr. Robinson holds a BS in Physics from The Cooper Union for the Advancement of Science and Art, and an MS in Physics from Franklin & Marshall. With 30 years in the semiconductor & electronics industry he has extensive experience in manufacturing, process engineering, and product/process design & development.

If you are not on our Chapter's regular email or FAX distribution list for meeting anouncements, you can easily be added! Please send an Email to Tom Tarter and let me know if you'd like email or FAX distribution. If you don't have Email, then please reply to 800 686-9366 (CPMT's 800 number), but please be advised that I would greatly prefer the Email route.

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Revised 30 June 2000