Components, Packaging & Manufacturing Technology Society

IEEE/CPMT Dinner Meeting:

Emerging Packaging Challenges:
The 2002 Semiconductor Packaging Roadmap
Joseph Adam, Conexant
(PDF file of talk -- 450kB)

Wednesday, April 10, 2002
  • Seated dinner served at 6:30 ($20 if reserved before April 6); $25 after & at door; vegetarian available)
  • Presentation (no cost) at 7:30.

    Ramada Inn

  • 1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale, (800) 888-3899 -- see map.


  • For dinner and/or meeting: by email to Tom Tarter
  • Please reserve for "presentation-only", even if not attending the dinner.

    There is an increased awareness in the industry that packaging has become a factor in electronic product cost, performance, and reliability. In some market segments packaging already represents 25% of the total system cost, limits the power and frequency of semiconductors, and is the dominate factor in product reliability. Based on the recently completed 2001 ITRS Assembly and Packaging roadmap projections the impact of packaging technology on future electronic systems will increase. To fully realize the benefits of emerging device technologies and develop competitive products for new applications the industry must increase both basic research and advanced development of packaging technology.

    With the increased impact of packaging on electronic products the industry will also need to adopt a more integrated approach to semiconductor, packaging and systems design. As a result the technology boundaries between semiconductor technology, packaging technology, and system technologies in electronics will blur. Today in many market segments package designs can no longer be executed independently of the chip and system; they must be considered concurrently in a system-level approach to minimize sub-optimization. The ability to exchange a broader range of complex design parameters between chip, package and system is required. Package design, to effectively address higher performance while reducing cost on a more diversified base of technology, is driving increasing complexity in design process, tools, and the need for more accurate materials information.

    To address these shifts in the industry needs and the 2001 ITSR Assembly and Packaging Chapter has been expanded to include new sections on package design, packaging materials, package reliability, MEMS packaging, optoelectronics packaging, and embedded passives. The objective of these new sections is to provide a basic overview of challenges and development needs in these areas. As each technology segment matures over the next several years more detail roadmap metrics will be developed by industry and incorporated in the Assembly and Packaging Roadmap.

    Speaker Biography
    Joe Adam is Vice President of Packaging and Test Technology at Conexant Systems Inc. where he is responsible for packaging and test strategy, package design, assembly process development, materials development, manufacturing sustaining engineering, DFT, test equipment development, and technology licensing. Under his leadership, Conexant has developed into a world leader in laminate based CSP, BGA, and MCM packaging for wireless and high performance network semiconductors. Prior to joining Conexant Mr. Adam led the Microprocessor Packaging and Test development effort for Alpha processors at Digital Equipment Corporation. He is presently Co-Chair of the Packaging Technical Working Group responsible for the International Technology Roadmap for Semiconductors and is a Member of the Strategic Advisory Committee for Unitive Electronics Inc.

    If you are not on our Chapter's regular email distribution list for meeting anouncements, you can easily be added! Please send an Email to Paul Wesling and let me know if you'd like email distribution.

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