Ramada Inn
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Although SoC brings the promise of lower-cost systems comprised of only a single chip, rather than a chipset and complex interconnect package or board, testing SoC systems constitutes a major challenge for both designers and test engineers, for a number of reasons. For example, with much of the inter-subsystem communication and data transfer occuring within the chip, there are often no external pins to use for testing particular functions. There may be mixed-signal designs, combining RF, analog, and digital -- even optical. And clock and data bus transfer rates can be in the GHz range, making the signals difficult to monitor and analyze in real time.
DFT (Design For Test) and BIST (Buit-In Self Test) techniques need to be employed early in the design cycle to enable both comprehensive and cost-effective testing of such complex devices. In this presentation, we introduce the leading DFT and BIST techniques used and the supporting industrial EDA tools and tester interfaces. The leading ATPG (Automatic Test Pattern Generation) algorithms will be analyzed and we will show how they can be used to ensure high fault coverage for the SoC under test. Finally, both MBIST (Memory BIST) and LBIST (Logic BIST) techniques will be explained.
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