Components, Packaging & Manufacturing Technology Society

IEEE/CPMT Dinner Meeting:

The Testing Issues and Approaches
Dr. Jacob El-Ziq
(PDF file of talk -- 400kB)

Wednesday, May 8, 2002
  • Seated dinner served at 6:30 ($20 if reserved before May 4); $25 after & at door; vegetarian available)
  • Presentation (no cost) at 7:30.

    Ramada Inn

  • 1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale, (800) 888-3899 -- see map.


  • For dinner and/or meeting: by email to Tom Tarter
  • Please reserve for "presentation-only", even if not attending the dinner.

    Many complex state-of-the-art chips are now designed and integrated as an SoC (System on a Chip), using various "cores" and IP (intellectual property) to comprise the full functionality needed for a particular product or application. The CPMT Society Chapter's May evening meeting will explore the nature of the verification problem facing the design and testing communities, and review some of the approaches being used.

    Although SoC brings the promise of lower-cost systems comprised of only a single chip, rather than a chipset and complex interconnect package or board, testing SoC systems constitutes a major challenge for both designers and test engineers, for a number of reasons. For example, with much of the inter-subsystem communication and data transfer occuring within the chip, there are often no external pins to use for testing particular functions. There may be mixed-signal designs, combining RF, analog, and digital -- even optical. And clock and data bus transfer rates can be in the GHz range, making the signals difficult to monitor and analyze in real time.

    DFT (Design For Test) and BIST (Buit-In Self Test) techniques need to be employed early in the design cycle to enable both comprehensive and cost-effective testing of such complex devices. In this presentation, we introduce the leading DFT and BIST techniques used and the supporting industrial EDA tools and tester interfaces. The leading ATPG (Automatic Test Pattern Generation) algorithms will be analyzed and we will show how they can be used to ensure high fault coverage for the SoC under test. Finally, both MBIST (Memory BIST) and LBIST (Logic BIST) techniques will be explained.

    Speaker Biography
    Jacob El-Ziq received his Ph.D. from Utah State University in Computer Engineering. He is an ASIC design, verification, test and training specialist. He has over twenty years technical and management experience in both system and chip companies, including Honeywell, Unisys and Sun Microsystems on the system side, and Toshiba and VLSI technology on the chip side. His EDA experience includes five years managing DFT, ATPG and chip planning products at Synopsys, Inc. Dr. El-Ziq is also an adjunct professor at both Santa Clara University and San Jose State University, teaching courses on ASIC design, synthesis and test.

    If you are not on our Chapter's regular email distribution list for meeting anouncements, you can easily be added! Please send an Email to Paul Wesling and let me know if you'd like email distribution.

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