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Glenn Narvaez from ChipPAC: "Stacked Die CSP Interconnect Challenges"
Technology demand for smaller and more inexpensive devices promotes use of existing technology optimization, which in turn supports the concept of stacked-die packaging as a viable solution. In order to accommodate quick-changing technological demands, stacked-die packaging requires advanced assembly techniques centered on a balance between interconnection (wirebonding) and mechanical stacking/thinning of the die. A brief review of the techniques and challenges that ChipPAC has encountered and developed for stacked die devices will be presented.

Dave Tovar from OSE-USA: "Stacked Die: Lessons and Directions"
OSE has been involved with multiple-die-stack programs since 1999. By year 2000 OSE was thinning wafers via backgrinding to 150 microns thick. Qualification of a 2-die-with-overhang stack program failed due to approximately 2% of the product dying during thermal gradient environmental tests. The failure mechanism was discovered to be microcracks on the bottom of the top die at the overhang junction. OSE researched and evaluated three different methods of thinning wafers: (a) by backgrinding, (b) by chemical etching, and (c) by atmospheric downstream plasma. Through an alliance with Tru-Si, an ADP wafer thinning organization, both organizations are working together in thinning wafers to 100 microns for a three-die stack program and to 75 microns for a four-die stack program. This talk will present design, manufacturing, quality, and reliability results on these programs.

Speaker Biographies

Glenn Narvaez is CSP Product Engineering Manager at ChipPAC, with 6 years' experience. He received his BS in Materials Science from MIT, and an MS (also in Materials Science) from Stanford University.

Dave Tovar is a veteran of the semiconductor industry, with over thirty five years experience at the management level in positions for domestic and foreign subcontractor organizations, with extensive skills in establishing strategic, developmental, operational, and logistic plans. His current position is as VP of Technology Development at OSE-USA. He has also served as President of PacTech-USA; Director at ChipPAC, GateField, and Synergy Semiconductor; and senior manager at VLSI Technology, Seeq, National Semiconductor, Qualidyne, Fairchild, and IBM. He holds a BA in German Literature and a BS in Analytical Chemistry, both from San Jose State University, and a MS in Chemistry, also from SJSU. He is a member of the American Chemical Society, the Components, Packaging, and Manufacturing Technology Society and the IEEE, and the Micro Electronic Packaging and Processing Engineers. Dave has written numerous Application Notes pertaining to product description, functionality, package development, and reliability for National Semiconductor, VLSI Technology, Synergy Semiconductor, and GateField Product Data Books. He has published and presented technical papers relative to wafer fabrication, electrical testing, advanced interconnect technologies, and product characterization. He was given the Best Technical Paper Award at the 1989 ITAB International Symposium.