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Wire Bonding to Advanced Copper, Low-k Integrated Circuits: the Metal/Dielectric Stacks, and Materials Considerations --
George Harman, Senior Scientist, National Institute of Standards and Technology (NIST)

Downloadable technical paper covering the subject of the presentation (PDF, 750kB)
Downloadable set of slides from the presentation (PDF, 1.5MB)

September 17, 2003 -- NOTE that this is one week later than our "usual" second-Wednesday meeting, and at a different place!
  • Seated dinner served at 6:30 ($25 if reserved before Sept. 13; $30 after & at door; vegetarian available)
  • Presentation (no cost) at 7:30.

    Wyndham Hotel in Sunnyvale (this meeting only)

  • 1300 Chesapeake Terrace (near Fwy 237 at Lawrence Expressway), Sunnyvale, 408-747-0999 -- see map.


  • For dinner and/or meeting: by email to Allen Earman
  • Please reserve for "presentation-only", even if not attending the dinner.

    There are four areas to consider when designing/implementing wire bonding to advanced ULSI-copper chips having damascene-trench copper metallization and low dielectric-constant polymers imbedded beneath them (Cu/Lo-k). These are: (1) the copper-pad top-surface oxidation inhibitor coating; metal /organic/ inorganic, (Problems in applying the copper protective and bondable coatings outside the wafer fab are also discussed), (2) the low dielectric constant materials and their properties, (3) under-pad metal/polymer stacks & support structures necessary for bondability and reliability, and (4) failure modes (typically delamination) experienced when bonding to the Cu/Lo-k structures.

    There are also various polymer/metallurgical interactions, resulting in long term packaged-device reliability problems, that can occur as the result of the wire bonding process over low modulus, Lo-k materials with barriers. These include cracked diffusion barriers, copper diffusion rates into the Lo-k polymers, cracking/spalling/crazing of the Lo-k materials, and bond pad indentation ("cupping"). Low-k polymer materials, with high expansion coefficients and low thermal conductivities, can also increase the stress and further extend any existing damage to barriers as well as increase the probability of electromigration of the copper lines. Many of the above problems have been previously encountered when bonding to pads over polymers (MCM-D, polymer buildup-layers on PCBs, PBGAs, flex circuits, etc.), and they share some of the same solutions. Well-designed Lo-k and the underpad structures should have no negative effect on bonding parameters and be invisible to the bonding process.

    For additional technical background in wire bonding, see the description for the one-day short course on Tuesday, September 16, "Principles in Wirebonding for Microelectronics."

    Speaker Biography
    George G. Harman is a Fellow of the National Institute of Standards and Technology's Semiconductor Electronics Division. He holds a B.S. in Industrial Physics from the Virginia Polytechnic Institute, an M.S. in Physics from the University of Maryland, and is a member of Sigma Pi Sigma and Sigma Xi. He is the author of over 50 publications, and has presented numerous seminars and short courses on wire bonding, packaging reliability and acoustic emission testing in electronics. Mr. Harman has authored two books on wire bonding. He has been nationally recognized with awards from IEEE, IMAPS and IEPS. Mr. Harman is a Fellow of the IEEE and IMAPS, as well as a member of the American Physical Society and ASTM. He served for the past 15 years as chair of the Fellows Committee of the IEEE's Components, Packaging & Manufacturing Technology (CPMT) Society and founded their VLSI Packaging Workshop.

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