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OVERVIEW:

Portable devices such as cell phones and PDAs are more likely to be dropped than affected by changes in thermal conditions. As a result, current reliability research has shifted from studying the effects of typical thermomechanical cycling to mechanical shock. Technical challenges arise from the complexity of lead-free solder metallurgies, printed wiring board finishes, and component metalizations.

Earlier studies have shown that intermetallic layers between lead-free solders and component metalizations are prone to fail in drop tests. Reactions between Ni(P)/Au coated pads on PWBs and solder alloys have been studied extensively. However, much less is known about the effects of component UBM (Under Bump Metalization) with different finishes and pad structures on lead-free and tin-lead assemblies under shock loading.

This talk will discuss the behavior of two UBMs used in wafer level chip scale packages on drop test performance, namely, (Al)Ni(V)/Cu metalization and electroless Ni(P)/Au metalization. A significant difference in the reliability performance of the components was observed: those with (Al)Ni(V)/Cu UBM were more reliable than those with electroless Ni(P)/Au UBM, regardless of the solder bump type, the solder paste, the surface finish of the boards, or the pad structure on the boards. The primary failure mode in the component side is the cracking of the interconnections along a brittle NiSnP layer between the electroless Ni(P) of high P-content and the solder alloy. Components with (Al)Ni(V)/Cu, on the other hand, fail by cracking along the [Cu,Ni]6Sn5 layer. On the board side, cracking happens in the porous NiSnP layer formed between the electroless Ni(P) metalization and the [Cu,Ni]6Sn5 intermetallic layer. Cracking happens predominantly on the component side due to three factors: 1. high stresses on the component side; 2. brittleness of the reaction layers; and, 3. strain-rate hardening of the solder interconnections. It will be shown that such failure mode differs from that typically observed in thermally cycled devices, where the nucleation and propagation of cracks are strongly enhanced by the recrystallization of the solder interconnects.

Speaker Biography

L. T. Nguyen is a Senior Engineering Manager in the Package Technology Group at National Semiconductor Corp, working on various aspects of wafer-level packaging, lead-free and halogen-free, thermal measurement and modeling, and design-for-manufacturability. He co-edited two books on packaging, and has over 190 publications. He has over 50 patents and invention disclosures. He is a Fellow of IEEE and ASME, and a Fulbright Scholar (Finland 2002). He is currently an Associate Editor for the CPMT Transactions on Advanced Packaging and a Guest Editor for the CPMT Transactions on Components and Packaging Technologies. He received two Best of Conference Awards (27th IEMT 2002 and InterPack 2005) and eight IMAPS and IEMT Best of Session Conference Awards. Other awards include the 2003 Mahboob Khan Outstanding Mentor Award from the Semiconductor Research Corporation in recognition of contributions to student mentoring, research collaboration, and technology transfer, and the 2004 IEEE CPMT Society's Outstanding Sustained Technical Contributions Award.