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Ramada Inn

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OVERVIEW:

In this presentation, we will first review where the technology is heading for multiple Gb/s high-speed links or I/O buses for networks and computer devices and systems. Then we will discuss why jitter and signal integrity have become the major challenges, as well as limiting factors for developing those high-speed and high-performance link devices and systems. Finally, we will cover the testing requirements and associated testing methodologies for jitter and signal integrity from a generic perspective, as well as from a practical application perspective, with examples of PCI Express and FB DIMM jitter and signal integrity testing.

Speaker Biography:

Dr. Mike Li is the Chief Technology Officer (CTO) with Wavecrest. Dr. Li pioneered a jitter-separation method (Tailfit) and the DJ, RJ, and TJ concept and theory formation. Currently he is Co-Chair for the PCI Express jitter standards committee. Dr. Li has more than 15 years of high-speed-related measurement instrumentation, testing, and analysis experience in applications including IC, microprocessor, clock and serial data communications for electrical, optical and wireless communication. He holds a BS in physics from the University of Science and Technology of China, a MSE in electrical engineering and a Ph.D. in physics from University of Alabama in Huntsville. He did his postdoc at University of California, Berkeley and worked there as a research scientist on high-energy astrophysics before he joined industry. Dr Li has published more than 70 papers in refereed technical journals, holds 4 patents and has 8 patents pending, and authored/edited one book on multiple Gb/s design and test.