IEEE/CPMT Luncheon Meeting, in the Santa Clara Valley:
"Package, Assembly and Thermal Challenges of Microprocessor Packaging"
Presentation Slides: "Package, Assembly and Thermal Challenges of Future Microprocessors" by Raj Masters (500 kB PDF)
-- Raj Masters, Corporate Fellow and Chief Technologist, Advanced Micro Devices
Thursday, February 22, 2007 Buffet lunch served from 11:45 - 12:15
($15 if reserved by Feb 19; $20 at door;
vegetarian available); presentation at 12:15.
Register & Prepay for lunch ($15) in one step from your PayPal account or Credit Card!
1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale, (800) 888-3899 -- see map.
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John Jackson, Analog Devices
As the demand for computing performance and density increases, the demand for packaging microprocessors is getting more complex. Computing speed and increased functionalities are achieved by reducing lithography features and increasing the number of transistors and number of metal layers. The performance is further enhanced by incorporating low-k dielectric films in the die. While the semiconductor makes leaps, it creates technological challenges and in some areas approaches technology barriers.
This talk describes the challenges of bumping at reduced pitch, packaging thermo-mechanical issues, and packaging fragile low-k films in a TCE-mismatched system. Discussions on assembly challenges that result from assembling large die in laminate packages will also be described. In summary, this talk discusses the inter-dependency between silicon technology, packaging Technology and reliability.
- Speaker Biography
Raj N. Master is a Corporate Fellow and Chief Technologist at Advanced Micro Devices.
Corporate Fellow is the highest technical position at AMD. Raj joined AMD in 1996. He was responsible for the successful transfer the IBM C4/BGA technologies to AMD and he set up high-volume manufacturing in Penang which has to date produced more then 200 million flip-chip assemblies. He led the Organic packaging development and manufacturing which is now in high volume production. As a part of that development he was responsible to select and develop package, component and material suppliers in the USA to support high volume production. He is also responsible for qualifying and providing technical direction to AMD's bumping and probing operations in Dresden, Germany. He led the selection and qualification of Unitive and bumping foundry and Amkor and ASE as assembly and test foundries. He provides technical guidance for equipment and processes for C4/BGA manufacturing lines in Suzhou, Penang and Singapore. He also provides technical expertise and guidance to product lines, failure analysis, and reliability and quality organizations within AMD. He manages an advanced packaging group involved in developing strategic enabling technologies. He is also manager of the Lead-Free program of AMD.
Raj joined AMD after spending 21 years at IBM. He was Senior Technical Staff member at IBM prior to joining AMD. He was responsible for packaging development and manufacturing as related to C4, Ball Grid Array, Column Grid Array, Board Level Reliability and Multi Layer Ceramic Substrate.
Raj has 36 U.S. patents issued to him and has published over 70 technical papers.
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