Thursday, February 22, 2007
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This talk describes the challenges of bumping at reduced pitch, packaging thermo-mechanical issues, and packaging fragile low-k films in a TCE-mismatched system. Discussions on assembly challenges that result from assembling large die in laminate packages will also be described. In summary, this talk discusses the inter-dependency between silicon technology, packaging Technology and reliability.
Raj joined AMD after spending 21 years at IBM. He was Senior Technical Staff member at IBM prior to joining AMD. He was responsible for packaging development and manufacturing as related to C4, Ball Grid Array, Column Grid Array, Board Level Reliability and Multi Layer Ceramic Substrate.
Raj has 36 U.S. patents issued to him and has published over 70 technical papers.
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