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"Semiconductor Manufacturing and Test Trends"
-- Dr. Erik Volkerink, Verigy

Thursday, May 22, 2008
  • Registration at 11:30 AM; Buffet lunch served from 11:45 - 12:15 ($15 if reserved by May 19; $20 at door; vegetarian available); presentation at 12:15.
    Ramada Inn
  • 1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale, (800) 888-3899 -- see map.


  • If you pay using our PayPal link, you are automatically registered for the lunch and meeting
  • Otherwise, for lunch and meeting, pre-register by email to Ed Aoki,
    Dr. Volkerink reviews the semiconductor Cycle of Innovation and what it means to semiconductor test. He’ll touch on advances in silicon technologies, reliability, the critical nature of ramping to yield, and the trends for integration. From there, he will delve deeper into the semiconductor test Cycle of Innovation, discussing innovations in test methods to address quality, throughput, and capital expenditures. Economics is a pervasive thread to the discussion.

    Speaker Biography
        Prof. Dr. Ir. Erik H. Volkerink is chief scientist for Verigy Ltd.'s Memory Test Solutions, and manages Verigy Labs Network. He is responsible for managing research programs, university relations, trend scanning, and IP. He is part of the Strategy Team led by Verigy's chief marketing officer. Dr. Volkerink also serves as a Consulting Assistant Professor in the Electrical Engineering Department of Stanford University and as Assistant Director of Stanford’s Center for Reliable Computing.
        Dr. Volkerink is an expert in semiconductor design and test, system architectures, and innovation management. He is recipient of the Best Paper Award from the Communicating Process Architectures (CPA) conference and a Best Paper Award nomination from the Design Automation Conference (DAC). He is active in many industry-wide activities, such as co-founder and General Chair of the ATE Vision workshop, the Corporate Track Chair of the International Test Conference (ITC), the Cost-of-Test Section Lead of the International Technology Roadmap for Semiconductors (ITRS). He was also a keynote speaker at the Future of ATE Workshop (FATE) as well as session chair and panelist at various conferences.
        Dr. Volkerink holds a Ph.D. in Electrical Engineering from Stanford University (supervised by Prof. McCluskey). He also studied Marketing and Finance at The Wharton School of Business. He received his master’s degree in Electrical Engineering from the University of Twente in The Netherlands, where he also studied Business Administration, Psychology, and Computer Science. He has completed management classes at The Boston Consulting Group, Heineken, American Management Systems, Royal Dutch Railway and Royal Dutch Telecom, and received a Rotary Youth Leadership Award.
        Previously, he worked with Verigy’s predecessor companies, Hewlett-Packard Company, Agilent Technologies, and with smaller companies in The Netherlands. In the early 1990s he obtained hands-on hardware/software experience while founding a software development organization.

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