IEEE/CPMT Luncheon Meeting, in the Santa Clara Valley:
"Embedded Passives: Methodologies and Opportunities for Implementation"
Presentation Slides: "Embedded Passives: Methodologies and Opportunities for Implementation" John Savic, Cisco Systems (1.2 MB PDF)
-- John Savic, Cisco Systems
Thursday, September 24, 2009 Registration at 11:30 AM; Buffet lunch served from 11:45 - 12:15
($15 if reserved by Sept. 21; $20 at door;
vegetarian available); presentation (no cost) at 12:15.
Embedded Passives (EP) has evolved over the last several years, demonstrating value as a versatile means for enhancing the functionality of the PWB by improving circuit performance, simplifying assembly processes and enabling product miniaturization. The value of EP technology has been demonstrated in numerous RF and logic circuit designs by incorporating thin film decoupling capacitors as well as Polymer Thick Film (PTF) resistors. The full potential of EP has yet to be realized due to a cacophony of industry offerings and much-displaced initial expectations. Success in implementation depends on selecting the appropriate application and diligent trade-off analysis during the design stage. This discussion will highlight some mainstream EP technologies and demonstrate the value that was realized through various product implementations.
- Speaker Biography:
John Savic was with Motorola for 16 years working on developing enabling technologies that enhance the functionality of HDI-PWB's. He holds numerous patents on HDI circuit and Embedded Passives (EP) manufacturing processes and has overseen the implementation of EP technology into over 80 million cell phone products. Currently John is with Cisco Systems where he is responsible for the development and implementation of advanced substrate technologies for improving the performance of BGA packages for next generation ASIC applications.
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