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    "3D IC Development and Supply Chain Collaboration"
    -- Suresh Ramalingam, Ph.D., Senior Director Advanced Package Design & Development, Xilinx Inc.

Presentation Slides: "3D IC Development and Supply Chain Collaboration"Suresh Ramalingam, Ph.D., Xilinx Inc. (2 MB PDF)
Watch Video of Talk: Link to WebEx Presentation (1 hour) -- will install/run the WebEx application on your PC.

Thursday, April 28, 2011

  • Registration at 11:30 AM; Buffet lunch served from 11:45 - 12:15 ($15 if reserved by April 26; $5 for fulltime students and currently unemployed; $5 more at door; vegetarian available); presentation (no cost) at 12:15.
    OVERVIEW:
        Driven by the ever-increasing internet bandwidth needs, 2.5D/3D packaging with TSV has gained a lot of attention, interest and momentum. Significant increases in interconnection density, lower latency and improvement in Bandwidth-per-watt makes this technology attractive. Starting with high-end CMOS image sensors and high-power applications, the technology looks to penetrate high-performance FPGA, graphics and mobile applications.
        In October 2010, Xilinx announced the Stacked Silicon Interconnect Technology that produces a new class of high-capacity, resource-rich FPGAs. These 28nm-based FPGA products are slated to go into production in early 2012. As the role of the FPGA becomes more dominant in system design, the designs grow larger and more complex, demanding higher logic capacity and more on-chip resources. To date, FPGAs have depended predominantly on Moore’s Law to respond to this need, delivering nearly twice the logic capacity with each new process generation. However, keeping pace with today’s high-end market demands requires more than Moore’s Law increases can provide.
        Xilinx has responded to these requirements with an innovative Stacked Silicon Interconnect Technology approach for building FPGAs that offer bandwidth and capacity one full generation ahead of when they otherwise become available using traditional Moore's law scaling. By combining through-silicon via (TSV) and micro-bump technology with its innovative ASMBL™ architecture, Xilinx is building a new class of FPGAs that delivers the capacity, performance, capabilities, and power characteristics required to address the programmable imperative. Xilinx stacked silicon interconnect technology combines enhanced FPGA die slices and a passive silicon interposer to create a die stack that implements tens of thousands of die-to-die connections to provide ultra-high inter-die interconnect bandwidth with far lower power consumption and one fifth the latency of standard I/Os.
        Technology development, supply chain and platform scalability were key focus areas to bring Stacked Silicon Interconnect Technology to fruition. Industry infrastructure development is in its early days with some IDMs, foundries and OSATs leading the way. Significant investment is required to enable the TSV, thin wafer handling, backside process and micro-bump assembly. Key technology challenges such as TSV Cu protrusion, KGD/PGD strategy, microbump yield and reliability, package reliability and thin wafer processing need to be understood and resolved. On the supply chain side the process flow and hand-off between foundry and OSAT is tricky, requiring careful technical and business assessment. This presentation will cover some aspects of Stacked Silicon Interconnect Technology and Supply Chain collaboration model.

    Speaker Biography:
        Dr. Suresh Ramalingam has 17 years experience in Semiconductor and Optical Packaging working at Intel, Scion Photonics, JDS Uniphase and Xilinx. He has managed teams in R&D, Package Design, Manufacturing and Business functions. As Senior Process Engineer at Intel (1994-1999) he developed from a clean slate HVM Underfill Equipment, Process and Materials for CPU Flip Chip on Organic Substrate. As Director of Packaging Materials at Scion Photonics from 2000-2004 he helped develop Array Waveguide, Variable Optical Attenuator, Wavelength Independent Coupler and Reconfigurable Optical Add Drop Multiplexer Packages which were used by major communication companies. JDS Uniphase acquired Scion Photonics in 2002. At Xilinx he managed Substrate Sourcing and Technology strategy from 2004-2009 and since then has been driving Package Design, TSV/3D Technology Development and Supply chain. He earned his Ph.D. and M.S. in Chemical Engineering from Massachusetts Institute of Technology and his B.Tech from Indian Institute of Technology, Madras. He has 13 US Patents issued and several publications including a Best Paper Award in Intel Journals.

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