IEEE Santa Clara Valley CPMT Society Chapter

"fcCuBE Technology: Expanding the Flip Chip Packaging Landscape" -- Dr. Raj Pendse, VP & Chief Marketing Officer, STATSChipPAC Inc.

• Buffet dinner served at 6:00 PM ($20 if reserved by Sept 12); $10 for fulltime students and currently unemployed engineers; $5 more at the door; vegetarian available)

• Presentation (no cost) at 6:45 PM (arrive by 6:35 PM)

  Please register in advance for this event, using our IEEE Council's DoubleKnot registration site.

  You may register yourself, plus others from your company/institution, for both dinner and presentation, or for only the presentation. You may make an on-line payment for the dinner, or arrange to pay at the door.

PLEASE RESERVE IN ADVANCE --
• For dinner and/or meeting: at the Doubleknot link above.
• Even if you're coming only for the presentation, we want you to sign up on our registration web site, so we can quicken the sign-in process and get everyone seated by 6:45 PM.

Biltmore Hotel

• 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara, (408) 346-4620 -- click map at right.

  
  

  OVERVIEW:

      Flip Chip packaging has rapidly evolved into a mainstream solution for a wide range of Computing and Mobile products by virtue of the compelling benefits in performance and small form factors. However, the continued adoption of flip chip technology presents several new challenges. The progressive increase in I/O density with new silicon (Si) nodes creates a widening gap between the escape routing density demanded by the Si device and the design rule roadmap for flip chip substrate technology. Concomitantly, the higher current densities resulting from this I/O density trend bring into play new long term failure mechanisms such as Electromigration. The trend towards Pb-free packaging necessitates bump and interconnect metallurgies that are mechanically damaging to the Si structure further exacerbated by the inherent fragility of the Si by virtue of the use of ELk/ULk (extra or ultra low k) dielectric materials in the newer Si nodes. Last but not the least, the continued deployment of flip chip packaging across a broader range of applications requires that the cost structure be in line with incumbent solutions comprising gold (Au) and copper (Cu) wire bonded packages which use laminate or lead frame substrates.
      fcCuBE^TM (flip chip with Cu column bump, BOL interconnection and Enhanced assembly processes) technology is a novel solution that systematically addresses the aforementioned challenges. It features the use of Cu column bumps to address the demand of high Si I/O and current densities in conjunction with a proprietary BOL (Bump on Lead) interconnect structure. The unique BOL structure enables remarkable improvement in escape routing density without stretching the substrate design rules while also achieving a dramatic reduction of mechanical stresses in the Si inner layers, thereby essentially eliminating the problem of damage to the Si structure. By virtue of the BOL structure and enhanced assembly processes, notably including Mold Underfilling (MUF), a majority of cost-challenged applications can be packaged in low cost packages with 2-layer laminate substrates comparable in cost to incumbent wire bond solutions.
      The key features of fcCuBE technology will be described in detail including the manufacturability and long term reliability of the package. An analysis of the scalability of the approach into the future and the fit of the technology in the overall application space relative to other approaches such as Fan-in and Fan-out Wafer level Packaging.

  

  Speaker Biography:
  

      Dr. Raj Pendse is the Vice President and Chief Marketing Officer at STATS ChipPAC where he is responsible for marketing and business development of the Company’s Advanced Technology products. Prior to joining STATS ChipPAC, Raj held various positions in R&D and Package Engineering at National Semiconductor Corp and Hewlett-Packard Labs. His work has spanned the gamut from packaging of high-end microprocessors, ASIC and graphics products to low-cost packaging solutions for logic and analog devices that find use in mobile phones and consumer products. His most recent focus has been on Flip Chip and 3D Wafer Level Packaging. Raj completed his BS in Materials Science from IIT Bombay with Top in Class Honors and his Doctorate in Materials Science from UC Berkeley.

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