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    "Memory Scaling and Its Potential Impact on Computing and Storage"
    -- Ed Doller, VP and Chief Memory Systems Architect, Micron Technology

Co-sponsored by the Computer, Electron Devices, and Circuits & Systems Chapters

WebEx Presentation: Ed Doller, Micron Technology (1:08 hours; WebEx player program will be installed)

First, download the Presentation Slides: "Memory Scaling and Its Potential Impact on Computing and Storage" Ed Doller, Micron Technology (1.5 MB PDF)

Thursday, September 22, 2011

  • Registration at 11:30 AM; Buffet lunch served from 11:45 - 12:15 ($15 if reserved by Sept 20; $5 for fulltime students and currently unemployed; $5 more at door; vegetarian available); presentation (no cost) at 12:15.
        As memory technologies scale current memory, usage models will be challenged. While new emerging technologies hold promise to solve the scalability challenge, it is unlikely that they will be "drop in compatible" with current technologies and thus will impact current memory hierarchies and utilization in the compute and storage segments. At the same time, lines are beginning to blur both in the compute segment and the storage segment as the debate over direct-attached storage is heating up - again. Ed Doller, VP of Micron's architecture research and development team, will explore the impact of scalability on current memory technologies, discuss what technologies may be next, and assess the impact of both of these on computer and storage architectures and on packaging options.

    Speaker Biography:
        Ed Doller is Vice President and Chief Memory Systems Architect at Micron Technology. Mr. Doller joined Micron in May 2010 from Numonyx where he served as Chief Technology Officer after its formation in 2008. Before Numonyx, Mr. Doller had a variety of roles in the Flash memory group at Intel, and then was appointed its Chief Technology Officer in 2004. Prior to Intel, he held several key positions at IBM in East Fishkill, N.Y., all in advanced semiconductor memories.
        Mr. Doller earned a Bachelor of Science degree in computer engineering from Purdue University. He has more than 27 years of experience in semiconductor memories, holds multiple patents, is a co-author of the IEEE floating gate standard, and is a frequent keynote speaker at memory conferences.

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