IEEE Santa Clara Valley CPMT Society Chapter
"Fine-Grained 3D Integration"
-- Deepak Sekar (speaker), Brian Cronquist and Zvi Or-Bach, MonolithIC 3D Inc.
Presentation Slides: "Fine-Grained 3D Integration" (700 kB PDF)
WEDNESDAY, January 11, 2012
PLEASE RESERVE IN ADVANCE --
- Buffet dinner served at 6:00 PM
($20 if reserved by Jan. 9); $10 for fulltime students and currently unemployed engineers; $5 more at the door;
- Presentation (no cost) at 6:45 PM (arrive by 6:35 PM)
Please register in advance for this event, using our IEEE Council's DoubleKnot registration site.
You may register yourself, plus others from your company/institution, for both dinner and presentation, or for only the presentation. You may make an on-line payment for the dinner, or arrange to pay at the door.
- For dinner and/or meeting: at the Doubleknot link above.
- Even if you're coming only for the presentation, we want you to sign up on our registration web site, so we can quicken the sign-in process and get everyone seated by 6:45 PM.
- 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara, (408) 346-4620 -- click map at right.
The first products using 3D packaging and TSV on the market are expected to have TSV diameters in the 5um range, while the International Technology Roadmap for Semiconductors predicts minimum TSV diameter in the 1um range between 2009 and 2015. While these micron-size TSVs are suitable for DRAM stacking atop logic, wide I/O DRAM, and other applications, we will show in this talk that getting through-silicon connections in the 10s of nm to 100s of nm range could have tremendous benefits. Approaches to obtain these small-size through-silicon connections will be described. This will include evolutionary approaches to extend today's TSV technology as well as fundamentally different monolithic 3D techniques.
- Speaker Biography:
Deepak Sekar is the Chief Scientist of MonolithIC 3D Inc. He received a B. Tech from the Indian Institute of Technology (Madras) in 2003 and a Ph. D. from the Georgia Institute of Technology in 2008. He held various engineering positions at SanDisk Corporation between 2006 and 2010, and conducted research on resistive memory technologies.
Dr. Sekar is the author of a book, an invited book chapter, 15 publications and 55 issued or pending patents. Awards he has received include a Key Innovation Award at MonolithIC 3D Inc. (2011), a Best Student Paper Award at the Intl. Interconnect Technology Conference (2008), a Best Paper Award at the IETE Technical Review (2009), an Intel Ph.D. Fellowship (2006-2008), a Motorola Electronic Packaging Fellowship Award at the Electronic Components and Technology Conference (2008), two Inventor Recognition Awards from the Semiconductor Research Corporation (2006, 2009) and the National Talent Scholarship from the Government of India (1997-2003). In addition, MonolithIC 3D Inc.ís technology was selected as a finalist for the "Best of West", which recognizes the three most important product and technology developments among the 746 exhibitors at Semicon West. He serves as a Program Committee Co-Chair at the International Interconnect Technology Conference and as an Advisory Board Member at 3D InCites.
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