IEEE Santa Clara Valley CPMT Society Chapter
"Cost Versus Reliability Tradeoffs for Stacked Devices"
-- Steve Steps, Senior Director of Wafer Level Burn-In & Test, Aehr Test Systems
Presentation Slides: "Die Stacking: Cost and Reliability Implications" (400 kB PDF)
WEDNESDAY, November 14, 2012
PLEASE RESERVE IN ADVANCE --
- Buffet dinner served at 6:00 PM
($20 if reserved by Nov 12) ; $10 for fulltime students and currently unemployed engineers
($5 more at the door;
- Presentation (no cost) at 6:45 PM (arrive by 6:35 PM)
Please register in advance for this event, using our IEEE Council's DoubleKnot registration site.
You may register yourself, plus others from your company/institution, for both dinner and presentation, or for only the presentation. You may make an on-line payment for the dinner, or arrange to pay at the door.
- For dinner and/or meeting: at the Doubleknot link above.
- Even if you're coming only for the presentation, we want you to sign up on our registration web site, so we can quicken the sign-in process and get everyone seated by 6:45 PM.
- 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara, (408) 346-4620 -- click map at right.
The industry demand for high feature-sets in very small, light products such as digital cameras, smart phones, medical devices and automotive electronics has driven a variety of high density packaging techniques. To achieve this high density, a wide variety of 3D packaging methods have been developed. The latest technique for stacking die is the Through Silicon Via (TSV) technology under development in many companies.
Although stacking has been very effective in improving the density of the resulting device, it has been decreasing the overall reliability of the device. Many of the same markets that are driving for high density are also becoming more reliability sensitive. It was easy to throw away a simple cell phone if it failed. However, modern smart phones are both much more expensive and contain more content that the user does not want to lose. Reliability demands are even higher if the device is being used for medial or automotive purposes.
This presentation will examine the reliability implications of stacked die. It will cover why reliable die ("Known Good Die -- KGD") is becoming more critical, what are the conditions that affect both the reliability and the need for KGD, and close with a case study of a technique for producing KGD: Wafer-Level Burn-In (WLBI).
- Speaker Biography:
Steve Steps has been the Senior Director of Wafer Level Burn-In and Test at Aehr Test Systems for the last 12 years. Prior to joining Aehr Test Systems, Steve worked at KLA and worked for 19 years at the Hewlett-Packard Company. Steve has had over 20 technical papers accepted at conferences around the world. Steve's educational background includes a BS degree in Electrical Engineering, a BS degree in Computer Science and a Masters Degree in Electrical Engineering.
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