(Last year's presentation slides, links to talks: www.cpmt.org/scv/meetings/cpmt1210w.html).

The 5th annual IEEE Santa Clara Valley SER Workshop provides a unique forum for component manufacturers, assembly houses, and electronic system manufacturers to exchange innovative ideas and recent results on the measurement, monitoring, and control of alpha emission from packaging materials and manufacturing processes. Built on the success of our workshops held in 2009 through 2012 (with over 100 attendees), this year's event continues to cover a wide range of areas and subjects critical to the control and mitigation of device soft error rates. Talks will cover the newest updates and advances for a wide range of areas including alpha emissivity measurement techniques and processes and impact on advanced low-k devices. Speakers will come from equipment makers, component manufacturers, and academic institutions. Sign up early!

Please register in advance for this event, using our IEEE Council's DoubleKnot registration site.

You may register yourself, plus others from your company/institution, for either the on-site Workshop, or for the live Webinar broadcast.

PLEASE RESERVE IN ADVANCE -- through Oct. 21 (Monday)
• This is a FREE event, and includes lunch. There is no fee for attending.
• Advance registration required, and on-site seating is limited to 40 people. Unlimited Web participation.
  
• On-site registration: 10:30 AM - 11:30 AM. Workshop talks from 11:30 AM - 5:00 PM
  
• On-line checkin: 11:00 AM PDT (1800 UTC) - 11:30 AM (1830 UTC), using your browser; links and login information will be provided in advance by email.
  
• Cost: none (includes equipment demos, light lunch, and drinks on-site) Location: On the campus of Cisco Systems:
  
  • Building 15, First Floor (Sunken Treasure Conference Room), 3750 Cisco Way, San Jose (MAP)
  • Enter through lobby

  • Also broadcast LIVE on the Internet, via WebEx (same registration procedure)

  OVERVIEW:
  

  Speaker / Company	Title and Abstract of Talk
  Mike Gordon, IBM TJ Watson Research Center	The Response of an XIA UltraLo-1800 Alpha Particle Counter to an External Beam of Protons Alpha counters have been shown to be sensitive to cosmogenic particles (n,p,? ,etc.) which contributes to the their background signal. The manner by which these cosmic events create background signals in alpha counters is starting to be understood. Last year, we published modeling results suggesting that incident neutrons could produce alpha particles via the (n,?) reaction both in the silicon substrate as well as in the counting gas and that this mechanism could contribute to the background in the counter. Recently, we embarked on a program to bombard one of our XIA UltraLo-1800 alpha particle counters with high energy protons from the Proton Therapy Center at MGH. In this work, we will discuss the results of the experiment including the proton flux detector that we built, the experimental results, and the implications for background reduction.
  Keynote: Prof. Blas Cabrera, Stanford University	Radon Induced Backgrounds in Search for Dark Matter WIMPs with Ge Detectors The SuperCDMS Collaboration is operating 15 advanced Ge detectors in the Soudan Underground Laboratory in northern Minnesota. In earlier versions of these experiments, we have been limited by low energy surface events from 210Pb decay betas and from 206Pb nuclei from 210Po decay. To reduce these backgrounds, we have reduced the Rn exposure of the detectors during fabrication and testing (now less than 0.2 210Po decays per 100 cm^2 surface area detector per day), and we have improved the surface event rejection by many orders of magnitude using and advanced interleaved detector design. The residual backgrounds are now below one event per kg of Ge per year.
  Adrian Evans, iROC	Techniques for Estimating the Effect of Combinatorial SER at the Chip Level In current technologies, it is generally assumed that the major contributors to chip-level SER are RAMs and flip-flops. Memories are now systematically protected by ECC and many designs make selective use of hardened flip-flops to mitigate the effect of flip-flop SEUs. As a result, the relative contribution of combinatorial SER is increasing. Estimating the effect of combinatorial SER is difficult because of the numerous masking factors which are difficult to estimate for a large SoC. In this presentation, we describe a hierarchical approach for estimating combinatorial SER that starts from the cell-level, builds up to the block-level and then to the SoC level. Simulation results for an open-source processor core are presented in order to validate the approach for small designs.
  Dinesh Maheshwari, Cypress Semiconductor	ECC Implementation to Reduce Accumulation of Memory Errors and Interface Channel Errors While the SER for memory is decreasing from one generation to next, the Bit Error Rate (BER) of high speed memory interfaces is increasing. This presentation will discuss how the ECC can be implemented to separate memory errors from interface channel errors.
  Ramya Ramarapu, Cisco Systems	A Study of Temperature Induced Polonium Diffusion on SRAM SER Performance Published work has reported heterogeneously distributed alpha emitters in a Sn sheet, with higher concentrations below the Sn surface. The alpha flux increase due to Po diffusion to the surface has also been documented. To assess possible impacts of temperature induced diffusion on SER, SRAM units were decapped and evaluated at several conditions. SER data collected showed no difference between background ambient conditions and exposure to ultra low alpha tin. SER increased when devices were exposed to tin containing significant Po, and increased still further when the higher alpha tin source was heated at 100° C for 1 hour The data presented indicate alpha flux changes due to Po diffusion can significantly influence SER in SRAM devices.
  Helmut Puchner, Cypress Semiconductor	Soft Error Mitigated Programmable System-on-a-chip (PSoC)   In this work we discuss the time required to make accurate alpha particle measurements of ultra-low emissivity (e< 2a/khr/cm2) samples. This time is related to the counter background, the level of radon adsorption and its decay, and counting (Poisson) statistics. We show examples of each using an early commercial version of the XIA UltraLo-1800 ionization counter.   The lowest emissivity we have measured to date, on a variety of known ultra-low alpha-particle emissivity samples, is about 0.3 a/khr/cm2. We have measured the alpha-particle emissivity of the same sample at two locations within our research laboratory; both underground, and on the second floor, and we observed ~2X difference in the number of alpha particles detected. We will present modeling results which show that neutron-induced reactions on silicon samples and in the argon counter gas can produce a measurable alpha-particle emissivity (that needs to be accounted for).   We will also present a review of Poisson statistics relevant for the time distribution between adjacent detected alpha-particle events. We show modeling results that demonstrate the variability of emissivity data one might obtain for repeated multi-day experiments, and use these simulated data to discuss the confidence intervals in the measurements. The effect of long or short measurement times on the confidence interval is discussed.
  Bharat Bhuva, Vanderbilt University	FIT Rates due to Alpha Particles at 40, 28, and 20 nm Bulk CMOS Technology Nodes In this presentation, experimental results for multiple flip-flop designs fabricated at 40, 28, and 20 nm bulk CMOS technology nodes will be presented. The basic design of the flip-flops is kept the same for all three technologies, allowing researchers to understand effects of scaling on alpha particle FIT rates.
  Panel Discussion with all speakers	Our authors and industry experts will discuss critcal issues related to alpha emissivity measurments, device performance, and test methodologies for advanced Si nodes.