IEEE Santa Clara Valley CPMT Society Chapter
"Design, Manufacturing and Performance of a 3D Random Access Memory Subsystem"
Presentation Slides: "Stacking Untested Wafers to Improve Yield" (900 kB PDF)
David Chapman, VP Technical Sales and Marketing, Tezzaron Semiconductor, Inc.
WEDNESDAY, November 13, 2013
PLEASE RESERVE IN ADVANCE --
- Buffet dinner served at 6:00 PM
($20 if reserved by Nov. 11th) ; $10 for fulltime students and currently unemployed engineers
($5 more at the door;
- Presentation (no cost) at 6:45 PM (arrive by 6:35 PM)
Please register in advance for this event, using our IEEE Council's DoubleKnot registration site.
You may register yourself, plus others from your company/institution, for both dinner and presentation, or for only the presentation. You may make an on-line payment for the dinner, or arrange to pay at the door.
- For dinner and/or meeting: at the Doubleknot link above.
- Even if you're coming only for the presentation, we want you to sign up on our registration web site, so we can quicken the sign-in process and get everyone seated by 6:45 PM.
- 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara, (408) 346-4620 -- click map at right.
The litany of problems associated with 3D ICs is long and ugly. Early adherents have been taking it on the chin for poor yields, high costs, impossibly difficult process steps, questionable reliability and up to now, relatively little gain for all their pain. 3D has been a technology-in-waiting for a decade. But despite excruciatingly slow progress towards volume manufacturing, a broad conviction that it ought to work and should produce amazing results has persisted.
This talk will cover the architecture and the manufacturing flow used to build a 3D random access 64Gb volatile memory subsystem that produces 4Tb/s of data bandwidth, with 7ns random access latency. This 3D implementation solves the problems with 3D and enables the production of ICs with outstanding yield and that pass thermo-mechanical tests with ease. Specific enabling technologies such as tungsten vias, DBITM wafer bonding and self-test and repair will described. Performance characteristics including power consumption will be presented.
- Speaker Biography:
After early career stops at HP, Apple and Olivetti focused on technical training, David Chapman became a full time memory geek by joining Mostek as an applications engineer and product planner in 1984. An 11 year tour at Motorola Memory Division managing Product Planning and Applications Engineering started in 1988, followed by 14 years at GSI Technology, starting in 1998 where he served as VP of Marketing and Applications Engineering. David has specialized in developing performance differentiated memory, mainly SRAM and Low Latency DRAM, and taken numerous leadership roles in memory and interface standardization efforts. David joined Tezzaron on July 1, 2013 as VP of Technical Sales and Marketing with a charter to expand Tezzaron’s reach into commercial markets.
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