IEEE Santa Clara Valley CPMT Society Chapter, with the MEMS & Sensors Chapter

"Tools for Thermal Analysis: Thermal Test Chips"
Tom Tarter, Package Science Services LLC

Wednesday, December 10, 2014

• Buffet dinner served at 6:00 PM
  ($25 for IEEE Members, $33 for non-members, if reserved by December 8) ;
  $10 for fulltime students and currently unemployed engineers
  ($5 more at the door; vegetarian available)

• Presentation (no cost) at 6:45 PM (arrive by 6:30 PM)

  Please register in advance for this event, using our CPMT Chapter's EventBrite registration site.

  You may register yourself, plus others from your company/institution, for both dinner and presentation, or for only the presentation. You may make an on-line payment for the dinner, or arrange to pay at the door.

PLEASE RESERVE IN ADVANCE --
• For dinner and/or meeting: at the EventBrite link above.
• Even if you're coming only for the presentation, we want you to sign up on our registration web site, so we can quicken the sign-in process and get everyone seated by 6:45 PM.
Biltmore Hotel

• 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara, (408) 346-4620 -- click map at right.

  
  

  OVERVIEW:

      Irrespective of if a device gets smaller, larger, hotter or cooler, some method is needed to determine the thermal behavior of a given chip/package/heatsink configuration. This is typically achieved by a combination of models and measurements and is useful in guiding the design team to the most cost-effective and reliable package and cooling solution. Most production chips have few or no available connections for temperature sensing and require complex biasing schemes and clock signals to achieve maximum power dissipation. Although some live devices may be evaluated for thermal performance, there is no clear indication of the on-chip temperature distribution. As we shrink feature size and combine more functions onto a given chip, the problem of temperature distribution becomes critical. Now, and as we move into more integrated chip functionality, temperature gradients and 'hot spots' must be considered to evaluate thermal performance and reliability. Another scenario that is difficult or impossible using live die is to determine the junction temperature of chips in various locations in a multi-chip application. In stacked, SiP, 2.5 and 3D packaging, the problem also includes measuring temperatures across the stack or array of chips. These factors, among others, can make using production die for thermal test expensive, inconclusive, or impossible.
      The alternative is to use specially designed thermal test chips. These chips make available power dissipating elements and temperature sensors in unit-cells, arrayable into various chip sizes. Sensors are addressable for each unit-cell on the array and resistor elements may be combined in various circuit configuratons to allow power variation anywhere in the array. Very high power density can be achieved in these die, limited only by interconnect current density and maximum temperature. Power supply and sensor reading does not require switching and allows simple connection and data collection. This chip set is a valuable tool in the modern design arsenal.
      The talk will focus on specifications and applications of the thermal test chip with examples to illustrate how the chip can be used to select and optimize cooling options, package design, cost, and time-to-market.

  Speaker Biography:
  

      Thomas (Tom) Tarter is a veteran and a leader in the electronic packaging characterization field. Starting at AMD in the early 80's, Tom was a principal architect of the Advanced Packaging Development Lab for AMD's Manufacturing Services Division. The lab enabled IC packaging development from concept, design and materials to performance, reliability and manufacturing processes. Tom has published over 30 papers on electronic packaging, lead industry standards and technical committees and is a senior member of the IEEE. Tom started Package Science Services LLC in 2008 to serve the need for advanced packaging design, analysis and process development.

  
  

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