Components, Packaging & Manufacturing Technology Society

IEEE/CPMT Dinner Meeting:

"Designing With Chip Scale Packages" --
Steve Bird, CEO, PCA Design, Inc.

Wednesday, September 10, 1997
Subsidized dinner ($10) served at 6:30, Presentation at 7:30.
Location: Pacific Fresh, 1130 N. Mathilda Ave, Sunnyvale, just North of US101 & CA 237 toward SF Bay
PLEASE RSVP by email to Harvey Miller, or call our CPMT hotline at 800-686-9366.

The mainstream design rules of 4-5 mil trace widths and spaces and 25 mil via pads for printed circuit board fabrication will readily support designs using fine and extra fine pitch quad flat packs. These QFPs have a pin count between 208 and 356 pins and yield pin densities between 45 and 75 pins per square inch. These same design rules will also support designs (sometimes with difficulty) using first generation peripheral ball grid arrays. These BGAs with a ball pitch of 1.0mm to 1.27mm yield pin densities closer to the 100 to 200 balls (pins) per square inch range. Full body array BGAs with pin densities in the 400 to 525 pins per square inch range present a formidable design challenge to everyone.

Design centers as well as their engineering customers are experiencing difficulty in completing designs that utilize high pin densities such as described above. Design times become less predictable and schedules out of control as we seek a solution. Our design most often becomes via-bound, and the time it takes to insert the necessary vias and traces increases dramatically. We relax the rules to 4 mil trace and space and slightly shrink our via size. We find that blind and buried vias help our cause and we may be able to complete the design. When the task becomes impossible, we begin to look for alternatives.

However, the challenge does not stop with these densities. A new generation of miniature BGAs, with a ball pitch of 0.5mm to 0.8mm are on the horizon. These small BGAs are also known as chip-scale packages or CSPs. These packages are attractive to customers because they are often not much larger than the die, mountable with equipment on the SMT line, detachable for rework, and offer pin densities in the 600 to 900 pins per square inch range and beyond. We must learn to design with them even though conventional substrates and design rules do not apply. We must seek alternatives.

Fortunately, while the packaging technology has been advancing, so has the interconnect technology and the alternatives we seek are becoming available. Depending on the interconnect technology chosen, next generation design rules will include 1 to 3 mil trace and space, 5 to 12 mil via pads with blind and buried vias inherent to the process. This class of interconnect is known as micro-via. We will study several new micro-via technologies such as laser drill, Surface Laminar Circuitry or SLC, Photo Link, DYCOstrate, Via and Custom Grid, etc. We will discuss how they allow us to design our substrates to accommodate CSPs.

Speaker: Steve Bird, Owner, PCA Design

If you are not on our Chapter's regular email or FAX distribution list for meeting anouncements, you can easily be added! Please send an Email to Richard Blish and let me know if you'd like email or FAX distribution. If you don't have Email, then please reply to 800 696-9366 (CPMT's 800 number) or FAX to me at (408) 741-3559, but please be advised that I would greatly prefer the Email route.

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Revised January 21, 1998