IEEE/CPMT Dinner Meeting:

"Designing With Chip Scale Packages" --
Steve Bird, CEO, PCA Design, Inc.

Wednesday, September 10, 1997
Subsidized dinner ($10) served at 6:30, Presentation at 7:30.
Location: Pacific Fresh, 1130 N. Mathilda Ave, Sunnyvale, just North of US101 & CA 237 toward SF Bay
PLEASE RSVP by email to Harvey Miller, or call our CPMT hotline at 800-686-9366.

The demand on circuit density is quickly being driven beyond that of today's pin densities.

Design centers as well as their engineering customers are experiencing difficulty in completing designs that utilize high pin densities such as described above. Design times become less predictable and schedules out of control as we seek a solution. Our design most often becomes via-bound, and the time it takes to insert the necessary vias and traces increases dramatically. We relax the rules to 4 mil trace and space and slightly shrink our via size. We find that blind and buried vias help our cause and we may be able to complete the design. When the task becomes impossible, we begin to look for alternatives.

However, the challenge does not stop with these densities. A new generation of miniature BGAs, with a ball pitch of 0.5mm to 0.8mm are on the horizon. These small BGAs are also known as chip-scale packages or CSPs. These packages are attractive to customers because they are often not much larger than the die, mountable with equipment on the SMT line, detachable for rework, and offer pin densities in the 600 to 900 pins per square inch range and beyond. We must learn to design with them even though conventional substrates and design rules do not apply. We must seek alternatives.

Fortunately, while the packaging technology has been advancing, so has the interconnect technology and the alternatives we seek are becoming available. Depending on the interconnect technology chosen, next generation design rules will include 1 to 3 mil trace and space, 5 to 12 mil via pads with blind and buried vias inherent to the process. This class of interconnect is known as micro-via. We will study several new micro-via technologies such as laser drill, Surface Laminar Circuitry or SLC, Photo Link, DYCOstrate, Via and Custom Grid, etc. We will discuss how they allow us to design our substrates to accommodate CSPs.

Speaker: Steve Bird, Owner, PCA Design

Steve Bird started PCA Design in his garage just over four years ago with one partner, and hardware on loan from Hewlett Packard. Today, PCA has over twenty employees, and offices in three states. PCA offers hardware, software, and design solutions to a wide range of customers.

Steve is an outstanding electrical engineer and is well respected in his field. For the past five years, Steve has worked closely with Happy Holden at Hewlett Packard and Merix to refine the DYCOstrate Design Process. Steve and PCA have more experience designing to this new and exciting manufacturing process than any other company in the world. Today, Steve is recognized as a worldwide evangelist for DYCOstrate technology, giving his presentations and seminars to major corporations both in the United States and Europe.

His leadership and motivational skills are outstanding, and his abilities to interface with the customer are unmatched. Steve is a dynamic speaker who brings life and excitement to his presentations. Steve has a style that not only informs the audience, but challenges them to reach for the best.

Steve has a BSEE from Cal Poly Pomona, and has begun post-graduate work at Stanford University. Steve holds two US Patents and has published numerous articles in trade magazines.