IEEE/CPMT Dinner Meeting:

"Wafer-on-Wafer Packaging" --
Dave Pederson, FormFactor

Wednesday, May 12, 1999
Subsidized buffet dinner ($10) served at 6:30, Presentation (no cost) at 7:30.
Location: FAZ restaurant, at the Four Points Hotel, on Mathilda, north of Hiway 237 and Fwy 101 junction, Sunnyvale
PLEASE RSVP (for dinner and/or meeting) by email to Rena Ayeras, or call our CPMT hotline at 800-686-9366.

OVERVIEW:
There is a growing disparity between the Moore's Law type cost decreases enjoyed by the semiconductor front end, compared with possible cost increases in the back end (package, test and assembly). The problems are particularly acute in memory modules, including Rambus DRAMs. FormFactor is commercializing the WOW (Wafer on Wafer) process, which will bring Moore's Law scaling benefits to the semiconductor back end. In this revolutionary process, a compliant interface is fabricated directly onto the wafer. This interface, called a MicroSpring^TM Contact, acts as the interface to the test and burn-in equipment, and as the chip to module interconnect. Memory modules have been built from DRAM, SRAM, and RDRAM, and subjected to reliability testing and electrical testing. The observed results are establishing new industry benchmarks for low cost, high reliability, and electrical performance. The WOW process may render obsolete traditional CSPs for memory modules.

In this talk, Dave will describe the overall WOW process flow, the interconnect structure and MicroSpring contact, and will report on reliability results, electrical test results, and cost estimates.

Dave Pederson has been the VP of MOST/WOW at FormFactor for the last 2 1/2 years. Before coming to FormFactor, he was employed as the VP of Engineering for Cubic Memory, developing a very dense chip stacking process. Previous to that Mr. Pedersen worked for two years with Cypress Semiconductor, and 15 years with AMD.