Components, Packaging & Manufacturing Technology Society

IEEE/CPMT Dinner Meeting:

"Integrated Passives" --
Harry Van Wickle, Intarsia; Dominick Richiuso, California Micro Devices

Wednesday, August 11, 1999
Subsidized buffet dinner ($10) served at 6:30, Presentation (no cost) at 7:30.
Location: FAZ restaurant, at the Four Points Hotel, on Mathilda, north of Hiway 237 and Fwy 101 junction, Sunnyvale
PLEASE RSVP (for dinner and/or meeting) by email to Rena Ayeras, or call our CPMT hotline at 800-686-9366.


Harry Van Wickle: Intergrated Passives for Telecommunications Applications
Among the major cell-phone suppliers, such as Nokia, Ericsson and Motorola, market share is contingent on the ability to deliver increased functionality in an appealing package with increased battery life and reduced cost. For example, the Nokia 6160 (the darling of the AT&T Wireless Digital OneRate plan) includes a built-in alphanumeric phone book, a calendar, links to voice-mail services, caller ID and paging functions, and even the ability to entertain with some rudimentary games. The device fits in a shirt pocket, and provides a 50-hour battery life in standby. This ever-increasing functionality is essential to attract new consumers.

A potentially more significant trend in RF is the addition of multiple bands and multiple modes in all wireless handsets and terminals. The concept of having a world device capable of operating on three or four continents at different frequencies -- and also of having multiple analog, CDMA and GSM/TDMA access -- is being commercialized in 1999 and is the future of wireless voice and data communications. In order to add this heterogeneity of access along with the many other functions required, designers must find ways to eliminate the discrete passive content in the RF section of cellular phones. To quantify the problem, in 1998 phone designs, Nokia has stated that in the RF section of its phones, passives represent 90% of the components, 85% of the space and 70% of the cost.

One company working on the elimination of discrete passives in various electronic applications is Intarsia Corporation. This talk examines Intarsia's multiple approaches to size, weight and cost reduction including:

  1. Packaged thin film integrated passives in either full Grid Array or Peripheral Chip Scale Packages form factors -- these packages are manufactured using Intarsia's wafer level chip scale package process. Intarsia also offers a plastic package for its integrated passives, but plastic does not provide the same performance enhancement and size, weight and cost reduction as CSP.
  2. Thin film integrated passive designs applied to module substrates. Eliminating the package and using the RF module substrate upon which to directly mask and stack up the thin film circuitry provides an additional level of cost, size, weight and performance enhancement. Intarsia is using glass and silicon as its current substrate materials. Development is in progress to move the Intarsia process to organic micro-via thin film substrates by the end of the year 2000.
  3. Adding active functions to thin film passives on Intarsia's substrates to manufacture more complex single functions such as VCO's and LNA's. RF Chipsets can also be added to the substrates to manufacture a complete RF front end in small form factor.

Dom Richiuso: Chip Scale Integrated Passive Devices for Wireless Applications
In today's modern electronic products, it is quite common for passive devices to outnumber active components by an order of magnitude. In many wireless applications where space is at a premium, such as cellular phones, the need for integrated passive devices is especially desirable. In addition, many of these applications require frequency responses that are difficult to achieve with traditional packaging and routing implementations.

A representative integrated circuit is described which incorporates complex thin film passive components in filtering applications. This Integrated Passive Device also incorporates active circuitry that provides ESD protection for the device port pins. The implementation described utilizes chip-scale packaging to provide a small form factor which greatly enhances device performance through the minimization of interconnect parasitics. Chip-scale packaging for this device provides optimal printed circuit board space utilization by incorporating all the circuit elements within the footprint of the die itself. The simulated and achieved device performances are presented. A discussion of the benefits and reliability considerations of chip-scale packaging is also presented.

Speaker Biographies:
Harry Van Wickle is a twenty-eight year veteran in semiconductor and disk drive manufacturing. 18 years of his career was spent in the Asia-Pacific region primarily in roles where he was responsible for Asian subsidiaries of American corporations. In Asia-Pacific, Mr. Van Wickle held top management positions at Texas Instruments, Fairchild Semiconductor, AT&T, and Micropolis Corporation and was assigned to Hong Kong, South Korea, Malaysia, Singapore and Thailand during his tenure.
Since returning to the United States in 1992 and prior to joining Intarsia, he has been Vice-President of Manufacturing at Cypress Semiconductor and President of Alphatec Electronics Corporation. Since December, 1997 Mr. Van Wickle has been President and Chief Executive Officer of Intarsia Corporation, an integrated electronic component design and manufacturing company located in Fremont, California.
Mr. Van Wickle also serves as a member of the Board of Directors of HMT Technology Corporation, a large Silicon Valley based disk media manufacturer. He holds a bachelor's degree from Hobart College.

Mr. Dom Richiuso is Director of Engineering for California Micro Devices, where he manages the development of the company's thin film integrated passive and CMOS integrated circuit programs. Over the past thirty four years, he has designed and managed the development and manufacture of numerous integrated circuits including IPD's, microprocessors, computer peripheral circuits, memories, interface circuits and custom industrial and consumer IC's. Prior to joining California Micro Devices he was President of Micro Silicon Associates Inc., a consulting firm providing MOS IC design and technology consulting services. He has held design and management positions at National Semiconductor, General Instrument Corporation and RCA. Mr. Richiuso received a BSEE from the City University of New York and a MSEE from the University of Pennsylvania.

If you are not on our Chapter's regular email or FAX distribution list for meeting anouncements, you can easily be added! Please send an Email to Rena Ayeras and let me know if you'd like email or FAX distribution. If you don't have Email, then please reply to 800 686-9366 (CPMT's 800 number), but please be advised that I would greatly prefer the Email route.

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Revised 9 July 1999