IEEE/CPMT Dinner Meeting, in the Santa Clara Valley:
"Factors Influencing IC Design Starts and Future Revenues"
-- Bryan Lewis and John Barber, Gartner Dataquest
Wednesday, April 11, 2007
Seated dinner served at 6:30
($25 if reserved by April 9; $30 after & at door;
Presentation (no cost) at 7:30.
$25 -- Register & prepay for dinner in one step from your PayPal account or Credit/Debit Card!
Ramada Inn1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale, (800) 888-3899 -- see map.
PLEASE RESERVE IN ADVANCE --
For dinner and/or meeting: by email to
Please reserve for "presentation-only", even if not attending the dinner.
The state of the ASIC and ASSP market can be described in one
statement: revenue up - design starts down. There are a number of key trends that must be explored to fully understand this short statement. Increasing revenue is being driven by rising chip selling prices (increased functionality per chip) coupled with rising unit volumes per design. This increasing functionality per chip or increasing integration is a two-edged sword, since that is also a primary reason for declining design starts. These big-picture trends can and will have a significant impact on the future of the IC packaging industry.
- Speaker Biographies:
John Barber is a research director for Gartner Dataquest's Hardware & Systems Semiconductor Applications & Devices Group. Mr. Barber is responsible for market analysis and forecast tracking for system-on-a-chip (SOC), system-level integration (SLI) and application specific standard products (ASSP).
Before joining Gartner Dataquest, Mr. Barber was product manager for NEC Electronics where he was responsible for product development and promotion of ASSPs targeting the digital consumer set top box, DVD recorder and audio/video for PC markets. Mr. Barber has served as a member on the board of directors and marketing working group chairman for the 1394 Trade Association. Mr. Barber has more than 10 years of experience in the semiconductor industry, working for Applied Materials,
Cisco Systems and NEC Electronics.
Bryan Lewis is a research VP and chief analyst for Gartner Research. Mr. Lewis joined Dataquest in 1985 and founded Dataquest's ASIC/SOC/FPGA research.
He has responsibility for tracking and evaluating market movements, forecasting markets, and tracking technology trends. He is a key speaker at numerous conferences and consults with a wide range of worldwide clients.
Mr. Lewis received a bachelor of science degree in marketing from the University of Oregon.
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